Federico Terraneo

Assistant Professor (RTD-B) at Politecnico di Milano - Dipartimento di Elettronica, Informazione e Bioingegneria (DEIB)
  • 1st floor, Building 20, Via Ponzio 34/5, Milano (MI), Italy, Europe, Earth, Solar System, Milky Way
  • Phone: (+39 022399) 3506
  • e-mail: federico.terraneo@polimi.it
  • dblp entry

About

Federico Terraneo has obtained the Master of Science Degree in Engineering of Computing Systems at the Politecnico di Milano with the thesis "Control based design of OS components", and the Research doctorate in Information Technology with the thesis "Thermal and energy management techniques for multi-core and many-core systems". Since 2008 he is the original designer, main developer and maintainer of Miosix, an operating system kernel targeting microcontroller-based embedded systems.


Research lines

Compilers for equation-based domain specific languages

Motivation

Modeling and simulation is a relevant application of computer science spanning from the embedded to the high-performance computing domain, with peculiar chracteristics which call for dedicated, domain-specific languages. This research line is focused on the modeling of dynamic systems, which are expressed in terms of Differential Algebraic Equations (DAE), and Ordinary Differential Equations (ODE). Dedicated languages have emerged to address this domain, such as Modelica, but existing translators exhibit signifcant scalability issues.

Achieved results

This new research line was started in 2018. Work is ongoing focused on benchmarking the current performance gap between declarative languages and hand-optimized simulation code, preliminary results have already been published on the topic. A roadmap has been proposed for the development of a compiler infrastructure for the Modelica language based on LLVM.

Outlook

Work is ongoing in the design of the Modelica compiler. Compared to existing approaches which translate Modelica code to C and then compile it with a C compiler, the proposed solution is to skip the C generation resulting in a Modelica to binary compiler. Moreover, the proposed approach will combine optimizations that are specific of the simulation domain (such as exploiting sparsity in the model, causalization and tearing) and optimizations specific of the computer architecture domain (such as loop optimizations, cache optimizations, vectorization and parallelization).

Time deterministic distributed embedded systems

Motivation

Many embedded systems need to meet Real-Time requirements which arise out of their interaction with the physical world. Long term research and industry trends such as Cyber-Physical Systems (CPS), Industry 4.0 and the Industrial Internet of Things (IIoT) are redefining the concept of embedded systems. One common aspect of these trends is the evolution from individual systems to networks of systems. This paradigm shift has thus exacerbated the need for design methodologies for Real-Time distributed embedded systems able to cope with unreliable connectivity such as wireless links.

Achieved results

Time determinism in distributed systems has the peculiar property that it cannot be solved through layering, unlike many other networking issues, because typical layering approaches achieve features such as reliability by repeating some operation, and this takes time. For this reason, a bottom-up approach has been followed, starting from the clock synchronization problem in wireless networks. Three major results achieved in clock synchronization are the design of FLOPSYNC-2, Reverse-flooding and Jitter-compensated VHT. FLOPSYNC-2 is a clock synchronization scheme that can compensate for nonlinear clock synchronization errors caused by temperature variations without the need for a temperature sensor. Reverse-flooding is a technique which employs constructive interference to measure propagation delays in a multi-hop network without requiring a spanning tree. A relevent byproduct of this approach is a coding technique that allows, under certain constraints, packets with different content to be transmitted concurrently and meaningfully merged by the radio channel. Also, the results above were achieved with off-the-shelf radio transceivers, without the need for a software-defined radio. Jitter-compensated VHT is a solution to synchronize a high-resolution and a low-energy timebase in the same embedded device, to improve energy efficiency without losing timing accuracy. Recently, research was widened to include protocols, with the design of TDMH, a MAC protocol that can leverage clock synchronization to provide bounded latency guarantees in wireless mesh networks. TDMH has been extended to become an entire networking stack capable of preserving time determinism.

Outlook

Future directions include the exploitation of the TDMH networking stack for real-time applications, and a study on the applicability of propagation delays measurements for localization. Adaptation of the devised solutions to higher bandwidth wireless network links is another envisaged direction.

Thermal management in computer architectures

Motivation

Today the semiconductor industry is facing increasing problems to continue delivering performance improvements at a pace that is now expected by its user base, as well as the general public. The failure of Dennard scaling results in an ever worsening power density increase, and has led to the dark silicon problem, where power and thermal constraints limit the number of transistors that can be switched at the maximum clock speed to an ever decreasing fraction. In such a scenario, thermal management and control is a fundamental design challenge that plays a key role in the performance optimization of computer architectures.

Achieved results

Federico Terraneo started working on this research line as part of his major Ph.D. topic. A first result has been the design and implementation of a thermal simulation platform that could simulate Globally Asynchronous, Locally sycnhronous (GALS) architectures with multiple DVFS actuators, and produce transient active silicon temperature maps. The simulation platform was then used to design a thermal control policy that can control fast temperature changes inside the active silicon, happening at a timescale of milliseconds, without severely impacting performance due to the policy overhead, for which a patent was applied and granted. After the Ph.D., the research shifted from simulation towards experimentation on real hardware. The simulation results and control policy were confirmed on Intel-based architectures, and this work received an outstanding paper award from the IEEE. A cooperation was started with the research group of Prof. David Atienza at EPFL on the thermal modeling and simulation of evaporative cooling solutions for high performance architectures. The need to simulate advanced cooling solutions exacerbated limitations in current thermal simulators for computer architecture. A new thermal simulation methodology making use of co-simulation has been designed, which led to the possibility to accurately model water cooling solutions. Validation of thermal models for water cooling has been performed in cooperation with the EPFL research group.

Outlook

Future directions include designing thermal policies taking advantage of evaporative and other nonstandard cooling solutions, as well as moving the research focus from the single computing platform to datacenters.